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XCR3256XL 256 Macrocell CPLD
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DS013 (v1.9) January 8, 2002
Preliminary Product Specification
Features
* * * * * Lowest power 256 macrocell CPLD 7.5 ns pin-to-pin logic delays System frequencies up to 140 MHz 256 macrocells with 6,000 usable gates Available in small footprint packages - 144-pin TQFP (120 user I/O pins) - 208-pin PQFP (164 user I/O) - 256-ball FBGA (164 user I/O) - 280-ball CS BGA (164 user I/O) Optimized for 3.3V systems - Ultra low power operation - 5V tolerant I/O pins with 3.3V core supply - Advanced 0.35 micron five layer metal EEPROM process - Fast Zero PowerTM (FZP) CMOS design technology Advanced system features - In-system programming - Input registers - Predictable timing model - Up to 23 clocks available per function block - Excellent pin retention during design changes - Full IEEE Standard 1149.1 boundary-scan (JTAG) - Four global clocks - Eight product term control terms per function block Fast ISP programming times Port Enable pin for additional I/O 2.7V to 3.6V supply voltage at industrial grade voltage range Programmable slew rate control per output Security bit prevents unauthorized access Refer to XPLA3 family data sheet (DS012) for architecture description
Description
The XCR3256XL is a 3.3V, 256 macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of 16 function blocks provide 6,000 usable gates. Pin-to-pin propagation delays are 7.5 ns with a maximum system frequency of 140 MHz.
TotalCMOS Design Technique for Fast Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technology and design technique. Xilinx employs a cascade of CMOS gates to implement its sum of products instead of the traditional sense amp approach. This CMOS gate implementation allows Xilinx to offer CPLDs that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 1 and Table 1 showing the ICC vs. Frequency of our XCR3256XL TotalCMOS CPLD (data taken with 16 resetable up/down, 16-bit counters at 3.3V, 25C).
140 120 100 80 60 40 20 0 0 20 40 60 80 100 120 140 160
*
*
* * * * * *
Typical ICC (mA)
Frequency (MHz)
DS013_01_102401
Figure 1: XCR3256XL Typical ICC vs. Frequency at VCC = 3.3V, 25C Table 1: Typical ICC vs. Frequency at VCC = 3.3V, 25C Frequency (MHz) Typical ICC (mA) 0 0.02 1 0.91 10 8.87 20 17.7 40 34.8 60 51.5 80 68 100 84.2 120 100.1 140 116.6
(c) 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS013 (v1.9) January 8, 2002 Preliminary Product Specification
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DC Electrical Characteristics Over Recommended Operating Conditions(1)
Symbol VOH VOL IIL IIH ICCSB ICC
(2)
Parameter Output High voltage Output Low voltage for 3.3V outputs Input leakage current I/O High-Z leakage current Standby current Dynamic current(3,4)
Test Conditions IOH = -8 mA IOL = 8 mA VIN = GND or VCC VIN = GND or VCC VCC = 3.6V f = 1 MHz f = 50 MHz
Min. 2.4 -10 -10 5 -
Max. 0.4 10 10 100 2 60 8 12 10
Unit V V A A A mA mA pF pF pF
CIN CCLK CI/O
Input pin capacitance(5) Clock input capacitance(5)
f = 1 MHz f = 1 MHz f = 1 MHz
I/O pin capacitance (5)
Notes: 1. See XPLA3 family data sheet (DS012) for recommended operating conditions. 2. See Figure 2 for output drive characteristics of the XPLA3 family. 3. See Table 1, Figure 1 for typical values. 4. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and unloaded. Inputs are tied to V CC or ground. This parameter guaranteed by design and characterization, not testing. 5. Typical values, not tested.
100 90 80 70 60 IOL (3.3V)
mA
50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 IOH (2.7V) IOH (3.3V)
Volts
DS012_10_041901
Figure 2: Typical I/V Curve for the XPLA3 Family
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DS013 (v1.9) January 8, 2002 Preliminary Product Specification
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XCR3256XL 256 Macrocell CPLD
AC Electrical Characteristics Over Recommended Operating Conditions(1,2)
-7 Symbol TPD1 TPD2 TCO TSUF TSU1 TSU2 TH(4) TWLH(4) TtPLH TR
(4) (4) (4)
-10 Max. 7.0 7.5 4.5 20 20 140 120 120 9.0 9.0 8.0 9.0 Min. 3.0 5.5 6.5 0 4.0 6.0 Max. 9.0 10.0 5.8 20 20 105 120 120 11.0 11.0 10.3 11.0 Min. 3.0 6.7 7.9 0 5.0 7.5 -
-12 Max. 10.8 12.0 6.9 20 20 88 120 120 13.0 13.0 12.4 13.0 Unit ns ns ns ns ns ns ns ns ns ns ns MHz s s ns ns ns ns
Parameter Propagation delay time (single p-term) Propagation delay time (OR array)(3)
Min. 2.5 4.3 4.8 0 3.0 4.5 -
Clock to output (global synchronous pin clock) Setup time (fast input register) Setup time (single p-term) Setup time (OR array) Hold time Global Clock pulse width (High or Low) P-term clock pulse width Input rise time Input fall time Maximum system frequency Configuration time(5)
(4)
TL(4) fSYSTEM(4) TCONFIG TINIT(4) TPOE(4) TPOD(4) TPCO(4) TPAO (4)
ISP initialization time P-term OE to output enabled P-term OE to output disabled(6) P-term clock to output P-term set/reset to output valid
Notes: 1. Specifications measured with one output switching. 2. See XPLA3 family data sheet (DS012) for recommended operating conditions. 3. See Figure 4 for derating. 4. These parameters guaranteed by design and/or characterization, not testing. 5. Typical current draw during configuration is 10 mA at 3.6V. 6. Output CL = 5 pF.
DS013 (v1.9) January 8, 2002 Preliminary Product Specification
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Internal Timing Parameters(1,2)
-7 Symbol
Buffer Delays
-10 Max. Min. Max. Min.
-12 Max. Unit
Parameter
Min.
TIN TFIN TGCK TOUT TEN TLDI TSUI THI TECSU TECHO TCOI TAOI TRAI TLOGI1 TLOGI2 TF TLOGI3 TUDA TSLEW
Input buffer delay Fast input buffer delay Global clock buffer delay Output buffer delay Output buffer enable/disable delay
-
2.5 2.2 1.0 2.5 4.5
-
3.3 2.8 1.3 2.8 5.2
-
4.0 3.3 1.5 3.3 6.0
ns ns ns ns ns
Internal Register and Combinatorial Delays
Latch transparent delay Register setup time Register hold time Register clock enable setup time Register clock enable hold time Register clock to output delay Register async. S/R to output delay Register async. recovery Internal logic delay (single p-term) Internal logic delay (PLA OR term)
0.8 0.3 2.0 3.0 -
1.3 1.0 2.0 5.0 2.0 2.5
1.0 0.5 2.5 4.5 -
1.6 1.3 2.0 7.0 2.5 3.5
1.2 0.7 3.0 5.5 -
2.0 1.6 2.2 8.0 3.0 4.2
ns ns ns ns ns ns ns ns ns ns
Feedback Delays
ZIA delay
-
2.8
-
3.7
-
4.4
ns
Time Adders
Fold-back NAND delay Universal delay Slew rate limited delay
-
6.0 2.0 4.0
-
8.0 2.5 5.0
-
9.5 3.0 6.0
ns ns ns
Notes: 1. These parameters guaranteed by design and/or characterization, not testing. 2. See XPLA3 family data sheet (DS012) for the timing model.
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DS013 (v1.9) January 8, 2002 Preliminary Product Specification
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XCR3256XL 256 Macrocell CPLD
Switching Characteristics
VCC
S1 Component R1 R2 C1 VOUT R2 C1 Values 390 390 35 pF
R1 VIN
Measurement TPOE (High) TPOE (Low) TP
S1 Open Closed Closed
S2 Closed Open Closed
S2
Note: For TPOD, C1 = 5 pF. Delay measured at output level of VOL + 300 mV, VOH - 300 mV.
DS013_03_102401
Figure 3: AC Load Circuit
7.5 7.4 7.3 7.2 7.1 7.0 6.9 6.8 6.7 6.6 6.5 6.4 6.3 1 2 4 8 16
+3.0V 90%
(ns)
10% 0V
TR
1.5 ns
TL
1.5 ns
Number of Adjacent Outputs Switching
DS013_04_042800
Measurements: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified.
DS017_05_042800
Figure 4: Derating Curve for TPD2
Figure 5: Voltage Waveform
DS013 (v1.9) January 8, 2002 Preliminary Product Specification
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Pin Descriptions
Table 2: XCR3256XL User I/O Pins TQ144 Total User I/O Pins 120 PQ208 164 FT256 164 CS280 164
Table 3: XCR3256XL I/O Pins (Continued) Function MacroBlock cell TQ144 PQ208 3 3 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 98 97 96 94 93 92 91 90 114 116 117 118 119 120 121 122 89(1) 88 87 86 17 18 19 20 21 22 24 25 26 27 197 196 195 194 193 192 190 189(1) 188 187 28 29 30(1) 31 33 FT256 G15 G13 F16 G14 G16 H13 H12 H15 H14 H16 D11 A11 E10 B12 C11 B11 A10 C10(1) A9 D9 J14 J15 J13(1) J16 L14 CS280 H17 H18 H19 J16 J17 J18 K16 K17 K18 L16 E14 D14 A14 C13 B13 A13 A12 C12(1) B12 D12 L17 L18 L19(1) M16 M18
Table 3: XCR3256XL I/O Pins Function MacroBlock cell TQ144 PQ208 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 106 104(1) 103 102 101 100 99 107 108 109 110 111 112 113 6 7 8 9 10 11 12 13 15 16 4 3 206 205 204 203 202 201 199 198 FT256 C16 F12 D16 E14 E15 F13 E16 F14 F15 G12 E13 D15 C13 A14 E11 A13 D12 B13 C12 A12 CS280 E18 E19 F15 F17 F18 F19 G16 G17 G19 H16 B19 B18 B17 A18 A17 C16 A16 E15 D15 A15
3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5
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DS013 (v1.9) January 8, 2002 Preliminary Product Specification
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XCR3256XL 256 Macrocell CPLD Table 3: XCR3256XL I/O Pins (Continued) CS280 M17 N16 N19 N18 N17 U10 T10 W11 U11 T11 W12 U12 T12 V13 U13 P16 P18 R19 R16 R18 Function MacroBlock cell TQ144 PQ208 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 77 75 74 66 67 68 69 70 71 72 2 1 143 142 141 140 45 46 47 48 49 65 64 62 61 60 59 58 57 56 55 153 154 159 160 161 162 163 164 166 FT256 M16 M14 N16 L12 P15 T12 R12 N11 T13 P12 R13 M11 T14 N12 R14 D3 C1 B4 E6 A4 C5 B5 D6 A5 CS280 R17 R15 T17 T16 U19 T13 W14 T14 R14 W15 U15 V15 T15 V16 W17 B1 C3 A4 B5 C5 A5 E6 D6 B6
Table 3: XCR3256XL I/O Pins (Continued) Function MacroBlock cell TQ144 PQ208 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 7 7 7 7 7 7 7 7 7 7 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 84 83 82 55 56 60 61 62 63 65 81 80 79 78 34 35 36 37 38 78 77 76 73 71 70 69 68 67 66 39 40 42 43 44 FT256 K15 K14 K16 K13 L15 R9 N9 T10 P10 R10 T11 N10 P11 M10 R11 K12 L16 M15 N15 L13 -
DS013 (v1.9) January 8, 2002 Preliminary Product Specification
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XCR3256XL 256 Macrocell CPLD Table 3: XCR3256XL I/O Pins (Continued) Function MacroBlock cell TQ144 PQ208 9 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 12 12 12 12 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 139 4(1) 5 6 7 8 9 10 11 138 137 136 134 133 132 131 12 14 167 151 150 149 148 147 146 145 144 142 141 168 169 170 171 172 173 175 176(1) 177 178 140 139 138 137 FT256 C6 D1 E4 D2 E3 E1 F4 F1 G5 E2 F3 B6 E7 A6 D7 B7 C7 C8 A7(1) D8 B8 F2 G4 G1 H1 CS280 A6 D2 D1 E3 E2 E4 E1 F5 F3 F4 G3 D7 C7 B7 A7 C8 B8 C9 B9(1) D10 C10 G2 G1 G4 H1 Table 3: XCR3256XL I/O Pins (Continued) Function MacroBlock cell TQ144 PQ208 12 12 12 12 12 12 12 12 12 12 12 12 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 14 14 14 14 14 14 14 14 14 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 15 16 18 19 54 53 49 48 47 46 45 20(1) 21 22 23 136 135 133 132 131 130 79 80 81 84 86 87 88 89 90 91 129 128 127(1) 126 124 FT256 H4 G2 J1 J3 H2 J5 P9 T9 P8 R8 N8 T8 P7 R7 P6 T7 J2 J4 K1(1) K3 K2 CS280 H3 H2 J2 J3 K2 K3 W10 T9 U9 T8 T7 W7 V7 U7 W6 T6 K4 L1 L2(1) L3 M1 -
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DS013 (v1.9) January 8, 2002 Preliminary Product Specification
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XCR3256XL 256 Macrocell CPLD Table 3: XCR3256XL I/O Pins (Continued) CS280 M3 M4 N1 N2 N3 V6 U6 R6 W5 T5 V5 U5 W4 U4 W3 P1 P2 P4 R3 R2 R4 T3 U1 Function MacroBlock cell TQ144 PQ208 16 16
Notes: 1. JTAG pins.
Table 3: XCR3256XL I/O Pins (Continued) Function MacroBlock cell TQ144 PQ208 14 14 14 14 14 14 14 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 25 26 27 28 44 43 42 41 40 39 38 37 29 30 31 32 34 123 122 121 120 119 92 93 95 96 97 98 99 100 101 102 118 117 115 114 113 112 111 110 FT256 L1 K4 L3 K5 M1 N7 R6 M7 T5 T6 R5 N6 T4 P5 R4 L2 M2 M3 N2 L5 P1 M4 R1
FT256 N3 T1
CS280 V1 U2
15 16
35 36
109 108
DS013 (v1.9) January 8, 2002 Preliminary Product Specification
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XCR3256XL 256 Macrocell CPLD
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Table 4: XCR3256XL Global, JTAG, Port Enable, Power, and No Connect Pins Pin Type IN0 / CLK0 IN1 / CLK1 IN2 / CLK2 IN3 / CLK3 TCK TDI TDO TMS PORT_EN Vcc TQ144 128 127 126 125 89 4 104 20 13(1) 24, 50, 51, 58, 73, 76, 95, 115, 123, 130, 144 PQ208 181 182 183 184 30 176 189 127 116(1) FT256 B9 A8 C9 B10 J13 A7 C10 K1 N1(1) CS280 A10 D11 C11 B11 L19 B9 C12 L2 P3(1)
5, 23, 41, 63, 74, 83, 85, E8, E9, F7, F8, F9, F10, A11, B10, C6, C14, 107, 125, 143, 165, G6, G11, H5, H6, H11, D13, D17, F2, J19, L4, 179, 186, 191 J6, J11, J12, K6, K11, P15, T18, U8, U14, V2, L7, L8, L9, L10, M8, M9 V9, V11 14, 32, 50, 72, 75, 82, 94, 134, 152, 174, 180, 185, 200 E5, F6, F11, G7, G8, G9, G10, H7, H8, H9, H10, J7, J8, J9, J10, K7, K8, K9, K10, L6, L11 E5, E7, E8, E9, E10, E11, E12, E13, G5, G15, H5, H15, J5, J15, K5, K15, L5, L15, M5, M15, N5, N15, R7, R8, R9, R10, R11, R12, R13 A1, A2, A3, A8, A9, A19, B2, B3, B4, B14, B15, B16, C1, C2, C4, C15, C17, C18, C19, D3, D4, D5, D8, D9, D16, D18, D19, E16, E17, F1, F16, G18, H4, J1, J4, K1, K19, M2, M19, N4, P5, P17, P19, R1, R5, T1, T2, T4, T19, U3, U16, U17, U18, V3, V4, V8, V10, V12, V14, V17, V18, V19, W1, W2, W8, W9, W13, W16, W18, W19
GND
3, 17, 33, 52, 57, 59, 64, 85, 105, 124, 129, 135
No Connects
-
1, 2, 51, 52, 53, 54, 103, 104, 105, 106, 155, 156, 157, 158, 207, 208
A1, A2, A3, A15, A16, B1, B2, B3, B14, B15, B16, C2, C3, C4, C14, C15, D4, D5, D10, D13, D14, E12, F5, G3, H3, L4, M5, M6, M12, M13, N4, N5, N13, N14, P2, P3, P4, P13, P14, P16, R2, R3, R15, R16, T2, T3, T15, T16
Notes: 1. Port Enable is brought High to enable JTAG pins when JTAG pins are used as I/O. See family data sheet (DS012) for full explanation.
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DS013 (v1.9) January 8, 2002 Preliminary Product Specification
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XCR3256XL 256 Macrocell CPLD
Ordering Information
Example:
Device Type Speed Grade
XCR3256XL -7 PQ 208 C
Temperature Range Number of Pins Package Type
Device Ordering Options
Speed -12 -10 -7 12 ns pin-to-pin delay 10 ns pin-to-pin delay 7.5 ns pin-to-pin delay TQ144 PQ208 FT256 CS280 Package 144-pin Thin Quad Flat Pack 208-pin Plastic Quad Flat Package 256-ball Fine-Pitch Ball Grid Array 280-ball Chip Scale Package Temperature C = Commercial I = Industrial TA = 0C to + 70C VCC = 3.0V to 3.6V TA = -40C to +85C VCC = 2.7V to 3.6V
Component Compatibility
Pins Type Code
XCR3256XL
144 Plastic TQFP TQ144 -7 -10 -12 C C, I C, I
208 Plastic PQFP PQ208 C C, I C, I
256 Plastic FBGA FT256 C C, I C, I
280 Plastic BGA CS280 C C, I C, I
Revision History
The following table shows the revision history for this document Date 01/21/00 02/10/00 05/03/00 11/20/00 12/11/00 01/17/01 03/05/01 Version 1.0 1.1 1.2 1.3 1.4 1.5 1.6 Initial Xilinx release. Updated Pinout table. Minor updates and added Boundary Scan to pinout table. Updated pinout tables; corrected note in Table 4 to read: "port enable pin is brought High". Updated specifications and pinout tables. Removed Timing Model. Added 256-ball Fine-Pitch Ball Grid Array Package. Revision
DS013 (v1.9) January 8, 2002 Preliminary Product Specification
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XCR3256XL 256 Macrocell CPLD
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Date 04/11/01 04/19/01 01/08/02
Version 1.7 1.8 1.9
Revision Added Typical I/V curve, Figure 2; added Table 2: Total User I/O; changed VOH spec. Updated Typical I/V curve, Figure 2: added voltage levels. Moved ICC vs Freq. Figure 1 and Table 1 to page 1. Added single p-term setup time (TSU1) to AC Table, renamed TSU to TSU2 for setup time through the OR array. Updated TSUF spec to match software timing. Added TINIT spec. Updated TCONFIG spec. Updated THI spec to correct a typo. Updated AC Load Circuit diagram to more closely resemble true test conditions, added note for TPOD delay measurement.
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